PCIe IP Verification Engineer

Overview

Senior Verification Engineer role focused on verifying the design and implementation of PCI Express (PCIe) controller IP.

What you'll do

• Verify PCIe controller ASIC design, architecture, and micro-architecture at IP/sub-system levels.
• Use state-of-the-art verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers, and scoreboards.
• Apply coverage-driven verification to develop test plans, tests, and verification infrastructure.
• Verify design correctness based on specification and implementation understanding.
• Collaborate with architects, designers, and pre/post silicon verification teams.

What you'll need

• 2+ years of relevant experience.
• B.Tech./M.Tech or equivalent experience.
• Experience in verification at unit/sub-system/SOC level.
• Expertise in Verilog and SystemVerilog.
• Experience verifying IP/interconnect protocols (e.g., PCI Express, USB, SATA).
• Experience with functional coverage and constrained random verification environments.
• Background in DV methodologies like UVM/VMM and exposure to industry-standard simulation/debug tools.

Nice to have

• Excellent knowledge of PCIe protocol (Gen3 and above).
• Good understanding of PCIe/CXL-based system-level architecture.
• Perl or Python (or similar) scripting and SW programming language experience.
• Good debugging and analytical skills.
• Good interpersonal skills.

Details

• Location/work mode indicated as #LI-Hybrid.