Analog Mixed-Signal Verification Engineer

Overview

Analog Mixed-Signal Verification Engineer to verify complex analog and mixed-signal IP blocks and subsystems using semiconductor process technologies.

What you'll do

• Develop and execute AMS verification plans for analog/mixed-signal IPs.
• Create behavioral models using Verilog-A/AMS and SystemVerilog.
• Build and maintain mixed-signal testbenches and run co-simulation.
• Collaborate with design and layout teams for verification coverage and post-silicon correlation.
• Automate regression testing and coverage analysis.
• Use tools such as Calibre, Synopsys CustomSim, and Cadence Virtuoso for PEX extraction, LVS/DRC signoff, and post-layout simulation.

What you'll need

• BS/MS in Electrical Engineering or related field.
• 2-4 years of experience in analog/mixed-signal verification.
• Proficiency in Cadence Virtuoso, Spectre, ADE-XL, SystemVerilog, and Verilog-A/AMS.
• Strong understanding of verification methodologies.
• Strong understanding of analog blocks and circuits.
• Strong collaboration skills to work with design and layout teams across process corners.

Nice to have

• Hands-on experience with Cadence AMS Designer, Spectre, Xcelium, and Virtuoso for co-simulation and regression testing.
• Proficiency in creating behavioral models using Verilog-AMS, SystemVerilog real types, and mathematical abstractions.
• Experience with real-number modeling.
• Experience with silicon debug and post-silicon validation.
• Familiarity with scripting languages (Python, Perl, Tcl).
• Strong communication and teamwork skills across analog, digital, and layout teams.