Staff Engineer Analog Mixed signal verification

Overview

AMS Verification Engineer for analog mixed-signal designs, developing and validating behavioral models and driving SystemVerilog assertion- and vector-based verification.

What you'll do

• Develop and maintain SystemVerilog real number modeling (SV RNM) and WREAL models for analog/mixed-signal IPs.
• Verify and correlate RNM/WREAL models against transistor-level schematics and analog simulation results.
• Create automated checkers and reusable verification components.
• Implement SystemVerilog Assertions (SVA) for protocol, functionality, timing, and correctness.
• Run SoC-level analog vector verification using DMS verification flows with UVM testbenches and RNM models.
• Analyze simulation results, debug failures, and ensure functional coverage.

What you'll need

• 5+ years of experience in AMS/Mixed-Signal Verification.
• Strong expertise in SystemVerilog RNM and WREAL modeling.
• Experience with UVM methodology and DMS verification.
• Hands-on experience building behavioral models for analog IPs and validating against schematic-level simulation.
• Experience with SoC-level AMS verification using RNM models and UVM environments.
• Strong understanding of analog/mixed-signal concepts including ADCs, LDOs, and buck/boost converters.
• Good understanding of EDA tools/simulators including Cadence Virtuoso Schematic Editor and Cadence Xcelium.

Details

• Location (ATS): Bangalore BTP.