Lead Layout Engineer

Overview

Lead Layout Engineer role in the Engineering Services Group at Qualcomm India, developing block, macro, or chip-level layouts and floorplans to project requirements, specifications and design schematics.

What you'll do

• Develop block, macro, or chip-level layouts and floorplans according to project requirements, specifications, and design schematics.
• Apply understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs.
• Conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues.
• Stay abreast of new verification methods.
• Work with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.
• Create technical documentation and presentations.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience; OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience; OR High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• Completed advanced degrees in a relevant field may be substituted for up to two years (Master's = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).
• 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).
• Hands-on experience on various Power Management (PMIC) Module layouts and physical verification using Calibre Verification suite.
• Extensive floor planning and signal planning skills in Cadence Virtuoso IC201 and above.
• Layout design for various analog circuits such as linear and switching regulators, ADCs, DACs, chargers, envelope trackers, APTs, high current powerFETs, OTAs, error amplifiers, etc.
• Strong understanding of submicron, deep-submicron, and High Voltage CMOS processes.
• Very strong analog layout fundamentals and basic electrical knowledge for layout development.
• Strong physical verification debugging capability using Calibre Verification Suite.
• Create area and parasitic efficient layouts, with strong problem-solving skills.
• Ability to perform in a dynamic, team-oriented environment, with well-developed organizational skills and the ability to multi-task.
• Strong communication skills for efficient delivery.
• Team player skills to work with geographically spread team members.

Nice to have

• SOI process knowledge.
• Scripting knowledge in SKILL/PERL/SHELL and hands-on knowledge of AI-based layout development flow.
• Graduation in Electrical or Electronics with 5+ years of experience (preferred).
• Diploma with minimum 8 years of hands-on layout development experience is also acceptable.

Details

• Location: Bangalore, India.