Lead PERC Rule Deck Development Engineer

Overview

Lead PERC Rule Deck Development Engineer driving PERC methodology, rule development, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability verification.

What you'll do

• Own and drive PERC rule development and methodology enablement for physical verification use cases.
• Lead development, enhancement, validation, and release of Calibre PERC rule decks for specified verification requirements.
• Translate technology, product, and signoff requirements into scalable PERC checks and reusable methodologies.
• Enable PERC flow across IP, block, subsystem, and SoC stages with integration to LVS/extraction/signoff flows.
• Debug complex PERC/LVS issues and provide root-cause analysis and closure recommendations.
• Develop automation scripts, regression suites, and reporting utilities for rule efficiency and traceability.

What you'll need

• BTech/BE/ME/MTech in relevant electronics/electrical/microelectronics/VLSI discipline.
• At least 10 years of relevant industry experience.
• Hands-on expertise in PERC rule development, debugging, validation, and production deployment.
• Proficiency in scripting/programming languages including TCL, Perl, Python, SKILL, and TVF/SVRF.
• Understanding of ESD fundamentals including HBM, CDM, system-level ESD models, and verification methodologies.
• Good understanding of analog/AMS design flows across schematic, layout, extraction, simulation, and signoff dependencies.

Nice to have

• Experience with Cadence Quantus or equivalent extraction/verification platforms.
• Familiarity with AMS verification and transistor-level RC extraction.

Details

• Location: Noida.