High Performance DSP core Implementation(Synthesis) Staff Engineer

Overview

Staff Engineer role for High Performance DSP core implementation focused on synthesis. You will work on physical synthesis, timing closure, and verification/signoff activities for ASIC/block development.

What you'll do

• Define, model, design, optimize, verify, validate, implement, and document IP development for block/SoC.
• Apply physical synthesis and synthesis methodologies using industry-standard tools.
• Write timing constraints, run STA, and perform timing closure and pipelining for performance optimization.
• Handle timing closure across multi-clock domain designs and support MCMM synthesis/optimization.
• Perform low-power implementation using UPF and apply power optimization flows/techniques such as clock gating.
• Work with design, DFT, and PD teams for netlist delivery and timing constraints validation; manage ECOs and formal verification.

What you'll need

• Experience in ASIC design, verification, validation, integration, or related work (Bachelors: 4+ years; Masters: 3+ years; PhD: 2+ years).
• 8+ years of hands-on experience in Synthesis and LEC.
• Strong knowledge of physical synthesis and synthesis methodologies with tools.
• Experience writing timing constraints for synthesis/STA, timing closure, and pipelining.
• Familiarity with MCMM synthesis and optimization.
• Good understanding of low-power design implementation using UPF.
• Scripting experience with Perl/Python and/or TCL.

Details

• Location: Noida, Uttar Pradesh, India.