Overview
Sr Engineer in NOC design focused on verification of next-generation infrastructure IPs for System-on-chip (SoC) used in smartphones, tablets, and other products.
What you'll do
- Plan and implement IP/cluster/formal verification flows for Infra IPs.
- Own DV test bench and associated collaterals (e.g., checkers, trackers, scoreboards, assertions, functional coverage).
- Develop test plans and test cases, and drive functional coverage closure at different test bench levels.
- Debug regression signatures and coordinate with design/SOC teams for failure debugging.
- Collaborate on code/functional coverage closure and follow up with stakeholders on code coverage.
- Develop and deploy scripts/tools for validation (e.g., Certitude, VC Formal, VPlan) and assist with post-silicon root cause analysis.
- Perform quality sign-off and maintain required documentation.
What you'll need
- Bachelor’s degree or higher in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years hardware engineering experience.
- Experience in verification architect/engineer responsibilities for Infra IPs (e.g., DDRSS, memory controllers) for SoCs.
- Expertise in UVM-based verification.
- Knowledge of ARM bus protocols, virtual memory concepts, and SoC system architecture.
- Experience developing monitors/scoreboards/sequencers using SystemVerilog and UVM to increase bug detection and resolution rate.
- Strong debugging, analytical, and problem-solving skills.
- Scripting proficiency (Python or Perl) for automation and C/C++/SystemC for performance models.
Nice to have
- Experience in designs optimized for low power (e.g., dynamic clock gating, logic/memory power collapse).
- Experience verifying designs meeting Automotive Safety Integrity Levels (ASIL).
- Post-si bring-up and HW-SW debug experience.
- Knowledge/exposure to silicon debug tool chains.
Details
- Location: Bangalore, India.
Read the full description and apply on the company’s own careers page.
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