NOC Design Verification Engineer

Overview

Lead design verification of complex AI, Networking, Datacenter, HPC and Interconnect IPs and sub-systems, independently driving verification from architecture understanding through signoff-quality closure.

What you'll do

• Independently own and execute IP/Sub-System DV from specification review to verification closure.
• Build reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions and coverage infrastructure.
• Drive verification planning, constrained-random verification, SVA, functional coverage closure and regression management.
• Debug RTL, protocol, architecture, performance and testbench issues, with root-cause analysis.
• Verify NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators or complex data movement fabrics.
• Perform performance verification, QoS validation, congestion analysis, scalability testing and system-level qualification.
• Develop Python, Shell, Perl or Tcl based regression automation, infrastructure and productivity tools.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• Expert in SystemVerilog (SV) and UVM.
• Strong expertise in verification planning, constrained-random verification, SVA, functional coverage closure, regression management and signoff methodologies.
• Proven ability to independently own and execute IP/Sub-System DV from specification review to verification closure.
• Strong debugging skills across RTL, protocol, architecture, performance and testbench issues.
• Deep protocol verification expertise in one or more of: PCIe (Gen4/5/6), USB (USB3.x/USB4), Ethernet (10G/25G/100G/400G+), CXL, or other high-speed serial/networking protocols.
• Strong understanding of AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.
• Proficiency in Python, Shell, Perl or Tcl.
• Familiarity with industry-standard simulators, debug tools, coverage tools, CI/CD workflows, emulation and verification automation frameworks.
• Strong collaboration, communication, technical leadership and execution skills.
• B.Tech/M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI or related disciplines from reputed Tier-1 institutions (IITs, NITs, IIITs, BITS, or equivalent).
• Relevant industry experience aligned with the position level in Design Verification, SV/UVM methodologies, protocol verification and architecture-driven validation.
• Proven history of technical ownership and successful delivery of complex IP, Sub-System or SoC verification programs.

Nice to have

• Experience with AI Scale-Up / Scale-Out Interconnects such as UAL, UMAC, eSUN, or equivalent accelerator cluster fabrics.
• Verification experience in SoC, AI/ML Accelerators, Networking, Datacenter, Multi-Die or HPC platforms.
• Exposure to SystemC/TLM modeling, performance modeling, emulation/prototyping and post-silicon correlation.
• Track record of delivering first-pass verification closure for complex IPs and subsystems.

Details

• Location: Bangalore, India.
• Equal opportunity employer; Qualcomm provides reasonable accommodations to individuals with disabilities during the hiring process.