Job description

Overview

Lead design verification for complex AI, networking, datacenter, HPC, and interconnect IPs and subsystems. Own verification from specification review through signoff-quality closure.

What you'll do

Build reusable SystemVerilog and UVM verification environments, agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.
Plan and execute constrained-random verification, regression management, coverage closure, and signoff activities.
Own IP and subsystem verification from specification review through verification closure.
Debug RTL, protocol, architecture, performance, and testbench issues and perform root-cause analysis.
Verify interconnects, memory and cache subsystems, AI accelerators, or complex data movement fabrics.
Validate performance, QoS, congestion, scalability, and system-level qualification.
Automate regressions and verification infrastructure using Python, Shell, Perl, or Tcl.

What you'll need

Bachelor's degree with 3+ years, master's degree with 2+ years, or PhD with 1+ year of relevant hardware engineering experience.
Expertise in SystemVerilog and UVM.
Strong verification planning, SVA, functional coverage, regression, and signoff experience.
Deep knowledge of at least one high-speed protocol, such as PCIe, USB, Ethernet, or CXL.
Understanding of AMBA protocols, including AXI, AHB, ACE, or CHI, and coherency architectures.
Strong debugging, collaboration, communication, technical leadership, and execution skills.
B.Tech or M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI, or a related discipline.

Nice to have

Experience with SoC, AI/ML accelerator, networking, datacenter, multi-die, or HPC platforms.
Exposure to SystemC/TLM modeling, performance modeling, emulation, prototyping, or post-silicon correlation.
Experience with AI scale-up or scale-out interconnects such as UAL, UMAC, or eSUN.

Details