NPU Design Verification Sr Engineer

Overview

Design verification engineer for Qualcomm's proprietary DSP/NPU IP, working with a global DSP design team to verify cores used across Qualcomm's multi-tier SoC roadmap.

What you'll do

• Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.
• Implement and improve System Verilog/UVM testbench architecture.
• Develop and deploy new verification methodologies and automation to continuously improve quality and efficiency.
• Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.
• Perform hands-on simulations and debug IP-level, subsystem-level and SoC-level fails and bugs.
• Complete all required verification activities at IP level to ensure high quality commercial success of products.
• Use assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration and emulation on a daily basis.
• Responsible for gate level simulation bring-up and gate level verification with timing simulations.
• Responsible for power aware RTL verification and gate level simulation.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience, OR Master's degree in a related field and 2+ years of Hardware Engineering or related work experience, OR PhD in a related field and 1+ year of Hardware Engineering or related work experience.
• 2+ years experience in processor/ASIC design verification.
• Solid background and understanding of Digital Design, Processor Architecture, Processor Verification and Power aware verification.
• Expertise in System Verilog Testbench Architecture and implementation.
• Gate-Level Simulation and Debug: 0-delay, timing annotated and power aware.
• Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence.
• Scripting/Automation Skills: Perl, Python, Shell, Make file TCI.
• Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.
• Should have excellent inter-personal and communication skills.

Nice to have

• Experience in writing C based and assembly level testcases.
• Exposure to power aware implementation and verification using UPF.
• Experience with advanced verification techniques such as formal and assertions.
• Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC, and hardware description languages (HDL) such as Verilog and SystemVerilog.
• Experience in verification of Processor subsystems.
• Experience in creating validation suite and building automation.

Details

• Location: Bangalore, India.
• Position for 2-8 years of experience.