Senior Engineer IP Verification - AMS Verification

Overview

Senior Engineer for IP Verification focused on AMS (analog and mixed-signal) verification.

What you'll do

• Verify analog/mixed-signal designs using AMS verification approaches.
• Debug complex analog/digital/mixed-signal circuits.
• Write Verilog model code, including Verilog-A/MS and RVM models.
• Build SPICE testbenches at Block and Fullchip level.
• Build COSIM/mixed-signal verification environments.
• Implement SV/UVM-based verification with SV/PSL assertions.

What you'll need

• 4-6 years of experience with a Bachelor’s in Electronics Engineering or related field, or a Post Graduate degree with 2-4 years experience.
• Hands-on experience with Virtuoso-based flows and related simulation tools.
• Experience with primesim/Finseim, Hspice, Xcellium, Simvision, and Waveview is expected.
• Hands-on experience writing Verilog models and Verilog-A/MS and RVM model writing.
• Experience building SPICE testbenches at Block and Fullchip level.
• Good scripting skills using Perl and Python (Python is a plus).
• Good communication, debugging skills, and ability to work in a team.

Details

• Location: Hyderabad - Phoenix Aquila, India.