Senior Power Engineer

Overview

Senior Power Engineer role in ASICS/ASIC engineering, focused on defining, designing, optimizing, verifying, validating, implementing, and documenting IP development for block/SoC.

What you'll do

• Define, model, and design digital and/or analog IP development for block/SoC.
• Optimize, verify, and validate RTL power and related implementations.
• Implement and document IP development processes and outcomes.
• Collaborate with cross-functional teams to determine product execution path.
• Debug RTL or gate-level power anomalies and identify root-cause scenarios.
• Use RTL power analysis and optimization tools to improve power efficiency.

What you'll need

• Have a Bachelor’s degree and 2+ years of ASIC design/verification/validation/integration experience, or a Master’s degree and 1+ year, or a PhD.
• 3+ years experience with a Bachelor’s in Computer Science/Computer Engineering or relevant technical field, or a Master’s degree.
• Understand RTL power optimization fundamentals including switching activity and clock/enable efficiency.
• Be familiar with RTL power analysis/optimization tools such as PowerArtist, PTPX, PowerPro, or equivalent.
• Know low-power design techniques including clock gating and power gating.
• Have knowledge of Emulation Power flow and methodology.
• Have strong Python programming skills for automation scripts and analysis flows.

Details

• Location: Noida, Uttar Pradesh, India.