Senior Principal Design Verification Engineer

Overview

Lead design verification for complex SoC, IP, and modem subsystem designs, shaping verification strategy, architecture and methodology across global engineering teams.

What you'll do

• Own verification strategy, planning, execution, and signoff for complex SoC/IP and modem programs.
• Architect scalable and reusable SystemVerilog/UVM verification environments.
• Develop verification plans, coverage models, assertions, scoreboards, and checking methodologies.
• Drive coverage closure and verification signoff using data-driven quality metrics.
• Debug complex design and verification issues and drive root-cause resolution across teams.
• Collaborate closely with architecture, design, firmware, validation, and software teams.
• Lead technical reviews and influence microarchitecture and design decisions.
• Mentor verification engineers and help drive organizational verification excellence.
• Coordinate effectively across global sites, time zones, and disciplines to ensure successful project execution.
• Drive methodology, automation, and productivity improvements across projects.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related field.
• 12+ years of Design Verification experience in semiconductor product development.
• Expert-level knowledge of SystemVerilog, UVM, SVA, constrained-random verification, and coverage-driven methodologies.
• Experience leading verification for complex SoCs, subsystems, or high-performance IPs.
• Strong debugging, root-cause analysis, and problem-solving skills.
• Proficiency in Python, Perl, Tcl, Shell, or similar scripting languages.
• Strong communication, leadership, and stakeholder management skills.

Nice to have

• Experience with USB, DisplayPort (DP), USB Type-C, USB Power Delivery (USB-PD), I2C, SPMI, and SPI protocols.
• Modem verification experience, including wireless communication subsystems, protocol stacks, and modem-related IPs, is a strong plus.
• Knowledge of formal verification, assertion-based verification, low-power verification (UPF/CPF).

Details

• Travel domestically and internationally as required (approximately 5%).
• Location: Bangalore, India.