SoC Verification Senior Lead Engineer

Overview

Senior SoC verification engineer to execute SoC-level and IP-level verification of complex SoCs, focused on ARM-based microcontrollers, low-power design and security IPs. Hands-on role in a fast-paced environment.

What you'll do

• Develop and own SoC-level and/or IP-level verification suites with coverage goals.
• Execute the verification plan according to the product specification and verification requirements defined by product architects.
• Develop, debug and run UVM-based verification environments for RTL/netlist simulation.
• Define and develop test cases in an appropriate verification framework.
• Create stimulus and assertions, run simulation, and debug test cases on design models (RTL, power-aware RTL, gate level, FPGA, emulation platform).
• Run regression, collect and analyze code and functional coverage.
• Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
• Collaborate with the team to develop and improve flows for maximum reuse and efficiency.
• Mentor junior team members while collaborating with design teams for issue resolution and sign-off.

What you'll need

• 12-15 years of experience in SoC/IP verification with participation in successful SoC tape-outs.
• Strong expertise in ARM-based microcontrollers and SoC-level verification, including C-based DV.
• Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification.
• Experience with low-power verification (UPF) is a must.
• Gate-level simulations and power-aware simulations is a must.
• Good working knowledge of assertions (SVA) and functional coverage.
• Good understanding of formal verification techniques and methodologies.
• Familiarity with both SoC-level and IP-level verification environments.
• Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
• Bachelor's or Master's in Microelectronics, Electronics or Electrical Engineering.

Nice to have

• Verification of multiple interfaces: SPI, I²C, UART, CAN, eSPI.
• Knowledge of Flash memory and security IPs.
• Experience with common analog IPs in microcontroller design (ADC, DAC, PLLs).

Details

• Location: Bangalore, India.