Senior/Staff Engineer- ESD Design

Overview

Join Marvell's Central Engineering team to establish ESD requirements and validate ESD solutions for Foundational IP, SerDes IP, and SOCs during the ESD qualification process.

What you'll do

• Provide co-design support with ESD simulations of circuits to maximize performance and ESD protection robustness.
• Perform ESD design reviews and provide technical guidance for analog, foundational IP, SOCs, and qualification test chips across technology nodes from 45nm to A14 on major foundry platforms.
• Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation and other industry methods and tools.
• Enable ESD protection schemes for analog design such as SerDes, including latch-up and transient latch-up, and ESD design verification and EDA tools.
• Continue developing ESD best practices for supported technologies.
• Develop and support EDA tools for ESD design checking.
• Develop circuits such as drivers, receivers, overvoltage protection circuits, fail-safe I/O, bandgap and voltage regulators.
• Develop IO circuits to customer specifications, including generation and delivery of final EDA views for the IP, such as biasing blocks, over-voltage/over-current protection circuits, regulators, amplifiers, switches and closed-loop feedback circuits.
• Provide support from initial design through failure analysis, root cause determination and development of corrective actions, working with Physical Design, Electrical Engineering and SOC teams.
• Derive design specifications from customer requirements.

What you'll need

• Bachelor's or master's degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields, and 3-7 years of related professional experience.
• Expertise in custom circuit design, handling layout effects in advanced FinFET process design rules, process variability and circuit reliability issues affecting power, speed, area and yield.
• Advanced knowledge of on-chip ESD protection circuit design.
• Advanced knowledge of CAD design tools such as Cadence and SPICE.
• Sufficient design experience to effectively review designs and communicate ESD design deficiencies to product design engineering.
• Advanced knowledge of ESD-relevant device physics such as snapback and other high-level injection phenomena and device operations.
• Full familiarity with industry ESD test standards and latest developments.
• Experience verifying ESD analysis for IP and SoC level using industry standard tools and methodologies.
• Experience with simulation using Cadence, including PEX, Monte Carlo and corner analysis.
• Effective communication across multiple sites and ability to work with multiple groups.

Nice to have

• Exposure and experience with custom ESD PERC code development.

Details

• Location: Bangalore.
• Eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers.
• Applicants must be eligible to access export-controlled information under applicable law; non-U.S. citizens, lawful permanent residents or protected individuals may be subject to an export license review prior to employment.
• Interviews must not use AI tools such as transcription apps, real-time answer generators or automated note-taking bots; use without prior instruction from the interviewer results in disqualification.