Senior/Staff NAND Design Rule Engineer

Overview

Drive and contribute to next-generation 3D NAND development within Process Integration by defining design rules and coordinating cross-functional actions across projects.

What you'll do

• Define physical design rules for current and future non-volatile memory technologies through production ramp.
• Coordinate with process integration teams to maintain accurate design rules.
• Evaluate layout and architecture feasibility with design teams.
• Develop automated and agentic solutions for design rule coverage, accuracy, and consistency.
• Investigate product and test structure failures involving layout and mask data.
• Support design rule checking for base and mask layers with physical verification teams.
• Define algorithms for generating mask data from drawn base-layer data.

What you'll need

• Master’s or PhD degree.
• At least 3 years of semiconductor industry experience in a listed process, yield, product, test-structure, or unit-process area.
• Knowledge of semiconductor device physics and VLSI silicon processing and integration flows.
• Python or other industry-standard programming experience, including agentic solutions.
• Design rule, layout, minor-layout, and CAD-tool experience.
• Knowledge of advanced semiconductor process flows and memory scaling.
• Strong written, verbal, and presentation communication skills.

Details

• Location: Hyderabad, Telangana, India.