Senior Technical Lead - CPU Physical Design

Overview

Lead physical design execution for next-generation CPU IPs, from floorplanning through signoff, with technical leadership across the physical design lifecycle.

What you'll do

• Lead physical design execution for CPU IPs from design planning through signoff.
• Provide technical leadership for floorplanning and design planning, placement and optimization, clock tree synthesis, routing and physical verification, timing closure, power and area optimization, and signoff readiness.
• Drive PPA convergence and deliver aggressive frequency, power, and area targets.
• Define and execute physical design strategies for advanced CPU architectures and technology nodes.
• Partner closely with Architecture, RTL, Circuit Design, DFT, CAD, Power, and Signoff teams to drive implementation success.
• Lead resolution of complex implementation, timing, congestion, and power challenges.
• Drive methodology improvements and adoption of best practices across multiple projects.
• Evaluate implementation tradeoffs and provide technical recommendations that influence architecture and design decisions.
• Mentor and guide engineers across the physical design organization.
• Collaborate with CAD teams to improve efficiency through automation, methodology enhancements, and AI-driven workflows.
• Support planning, estimation, risk assessment, and execution tracking for physical design deliverables.
• Contribute to hiring, technical interviews, and development of engineering talent.

What you'll need

• M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, VLSI, or a related discipline.
• 14+ years of industry experience in ASIC or CPU Physical Design.
• Proven experience delivering successful products through complete physical implementation and signoff cycles.
• Strong expertise in floorplanning and design planning, placement and optimization, clock tree synthesis, routing and closure, static timing analysis, signal integrity, power integrity and EM/IR, and physical verification.
• Hands-on experience with industry-standard implementation tools such as Synopsys Fusion Compiler, ICC2, Cadence Innovus, PrimeTime, StarRC, RedHawk, and Calibre.
• Strong scripting and automation experience using Python, Tcl, and Shell.

Nice to have

• Experience delivering high-performance CPU core, cache, fabric, or compute IP designs.
• Experience with advanced process technologies such as Intel 18A/14A, TSMC N3/N2, or equivalent.
• Deep understanding of physical design methodologies, advanced timing closure techniques, hierarchical implementation, variation-aware design methodologies, and power-aware implementation.
• Experience leading geographically distributed teams.
• Experience driving CAD methodology improvements and automation initiatives.
• Familiarity with AI, Machine Learning, and Agentic AI applications for design automation and productivity enhancement.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.