Power Architect – AI SOC

Overview

Drive end-to-end PPA (Power, Performance, Area) excellence for next-generation AI semiconductor chips, bridging front-end architecture and back-end physical design.

What you'll do

• Drive comprehensive SoC-level power and thermal management architecture.
• Influence microarchitecture, memory hierarchies, and dataflows to minimize dynamic and leakage power for AI inference and training workloads.
• Review and guide RTL implementation to ensure consistency with power and timing goals.
• Collaborate directly with Physical Design (PD) teams to refine area constraints, floorplanning, and multi-voltage domain structures.
• Develop, fine-tune, and build advanced Physical Design recipes (covering synthesis, placement, clock tree synthesis, and routing) tailored to achieve best-in-class PPA targets.
• Partner with EDA vendors and internal teams to drive the adoption and customization of advanced power analysis tools (e.g., PowerArtist, PrimePower, Joules).
• Develop custom scripts and design workflows where standard tools fall short.
• Lead PPA analysis and trade-off discussions across RTL, architecture, and PD teams.
• Act as the central hub to resolve complex bottlenecks and ensure the final silicon meets strict power budgets.

What you'll need

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of semiconductor experience with a deep focus on SoC architecture, low-power RTL design, and Physical Design (PD) implementation.
• Proven track record of delivering complex, high-performance silicon (AI accelerators, GPUs, or advanced SoCs) under stringent PPA constraints.
• Hands-on expertise with power intent (UPF/CPF) and industry-standard power estimation/analysis tools.
• Strong scripting and automation skills (Python, Tcl, Perl) for customizing EDA tool flows and PPA data analysis.

Details

• Location: Bengaluru, Karnataka, or throughout India (remote-friendly with travel).