Silicon Package Design Engineer

Overview

Silicon Packaging Design Engineer role within Intel's Assembly and Test Technology Development (ATTD) Design group, performing end-to-end substrate design and routing studies for advanced silicon packaging solutions.

What you'll do

• Develop physical layout designs for silicon packages, assembly test chips, and Intel's EMIB (Embedded Multi-die Interconnect Bridge) technologies.
• Collaborate with customers and electrical engineers to optimize signal integrity and power delivery.
• Create bump patterns and placements while adhering to design rule requirements.
• Perform signal routing planning and power grid placement to meet electrical and manufacturing standards.
• Conduct layout verification processes, including routing checks, connectivity validation, DRC (Design Rule Check), and electromigration analysis.
• Provide feedback on feasibility studies and implement customer enhancement requests.
• Resolve design and methodology challenges related to layout design tools and workflows.
• Document design processes and maintain collateral in product lifecycle management systems.

What you'll need

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a STEM-related field with 1-6 years of hands-on experience in silicon packaging design, demonstrated through academic projects, internships, coursework, or training OR a Master's degree in a related field with no prior professional experience.
• Proficiency in EDA tools such as Cadence or Siemens for package/PCB design.
• Familiarity with programming languages such as Python, Perl, Linux, and/or SKILL.
• Strong understanding of electrical field theories and electronic fundamentals.

Nice to have

• Excellent written and verbal communication skills.
• Attention to detail and a customer-oriented mindset.
• Highly motivated and results-driven with a passion for innovation.

Details

• Job type: Experienced Hire.
• Shift 1 (India).
• Location: Bangalore, India.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.