SoC Verification Engineer - Design for Debug/Design For Test

Overview

Join Intel's Design Development Group as an SoC Validation Engineer focused on Design for Debug (DFD) and Design for Test (DFT), working on pre-silicon validation of future Intel SoCs or IPs.

What you'll do

• Validate Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA.
• Validate Design for Test features such as TAP, SCAN and so on.
• Develop testcases in Python for the Emulation platform.
• Provide post-silicon support.
• Create test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learn the Power Management, Memory and SoC debug architecture and microarchitecture by debugging failures to the root cause.
• Develop and utilize debug and validation tools and/or methodologies to implement validation plans and ensure a solid design.
• Participate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL models.
• Develop debugging tools and software.
• Work with pre-silicon and post-silicon validation teams to improve debug features and tool suites, and with post-silicon validation software teams on debug tool validation and silicon enabling.
• Pioneer new debug tools and flows, review and publish architectural specs, and support next-generation silicon enabling on system platforms.
• Work with multi-function teams and sites to implement and validate debug solutions.

What you'll need

• A BS or MS in Computer Science, Computer Engineering or Electrical Engineering.
• Extensive pre-silicon and post-silicon track record of driving debug tool enabling and validation, improvements, and getting them adopted by others.
• Proven record of working across validation teams to solve problems.
• Expert knowledge of HW and SW interaction and debug to root cause.
• Experience working across validation, architecture, SW, design teams and Post-Si to resolve debug issues.
• Minimum 4 years of experience with DFD/DFT.
• Minimum 8 years of experience writing validation plans and software to implement those validation plans.
• Minimum 4 years of experience with programming languages/scripting: C, Python, Verilog and SystemVerilog.
• Minimum 4 years of experience with computer architecture.

Nice to have

• 4+ years of experience with Design for Debug/Design for Test.
• 4+ years of validation or testing experience.
• 3+ years of experience with industry standards such as ATB, CoreSight, JTAG.
• Experience with Tessent tools.
• 2+ years of experience in emulation and post-silicon support.

Details

• Location: India, Bangalore.
• Shift: Shift 1 (India).
• Job type: Experienced hire.
• Work model: Hybrid, splitting time between on-site at the assigned Intel site and off-site.