SR ENGINEER, DDEG Design Methodology

Overview

SR Engineer for DRAM Design Verification methodology, focusing on full-chip gate-level custom design verification and end-to-end analysis with low-power/power management technologies.

What you'll do

• Use AI-based tools, agentic workflows, and automation to accelerate verification cycle time.
• Support DRAM design verification by simulating, analyzing, and debugging pre-silicon block-level/full-chip designs.
• Develop test cases/stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Build and maintain test benches/test vectors and run regressions for coverage analysis.
• Improve debug efficiency across simulation and silicon learning loops.
• Validate AI outputs against assumptions, specs/standards, simulations, waveforms, assertions, and coverage reports.
• Develop verification methodology and verification environments for advanced DRAM and emerging memory products.

What you'll need

• Experience in SystemVerilog and PLI coding.
• Experience with UVM test bench verification.
• Experience in DRAM, SRAM, or other memory-related fields.
• Experience in AMS verification and co-simulation.
• Good communication and debugging skills and ability to work well in a team.
• Analytical capability for complex CMOS and/or gate-level circuit designs.
• Bachelor’s or Post Graduate degree in Electronics Engineering or related engineering field.

Details

• Works with design and verification team members across the globe.
• Design categories include DDR4, LPDDR4, DDR5, and LPDDR5 up to 6400MT/s.