Sr Principal Engineer

Overview

Lead architecture, implementation, verification, and validation of DFT features for automotive in-vehicle networking devices, including pre- and post-tapeout activities.

What you'll do

• Define and implement Scan, JTAG, MBIST, and LBIST strategies.
• Lead digital subsystem integration and perform scan insertion.
• Generate ATPG patterns and improve fault coverage.
• Drive post-silicon validation and debug to root-cause failures.
• Coordinate with physical design and test engineering teams on timing closure.
• Ensure test patterns are operational when silicon arrives.

What you'll need

• 10+ years of industry experience in SoC DFT implementation, verification, timing closure, test coverage, and silicon bring-up.
• B.S. or M.S. in Electrical or Computer Engineering, or a similar degree.
• Proficiency with Tessent, Cadence, or Synopsys EDA tools.
• Strong knowledge of scan insertion, ATPG, MBIST, LBIST, boundary scan, JTAG, and test compression.
• Strong Verilog or SystemVerilog skills for RTL test logic and wrappers.
• Knowledge of STA and DFT-specific SDC timing constraints.
• Expertise in Tcl, Python, or Perl automation.

Details

• Location: Noida, India.