Sr Principal SoC DFT Engineer

Overview

Senior Principal SoC Design-for-Test Engineer serving as a senior technical authority for complex custom SoC designs, defining DFT strategy and architecture and driving resolution of critical test problems from concept through high-volume manufacturing.

What you'll do

• Define DFT strategy, architecture, methodology, and signoff criteria for complex SoCs and multiple interdependent technical areas.
• Lead high-impact DFT initiatives spanning planning, risk management, execution, manufacturing readiness, silicon quality, and test cost.
• Architect scalable solutions for scan and ATPG, compression, memory test and repair, logic BIST, test access, boundary scan, IJTAG, and mixed-signal test.
• Establish readiness and signoff frameworks, close critical risks, and provide evidence-based recommendations to engineering and program leadership.
• Solve critical DFT problems of exceptional complexity and establish reusable approaches across products and teams.
• Lead cross-functional resolution of issues involving architecture, RTL, DV, PD, firmware, product engineering, manufacturing test, and post-silicon teams.
• Drive DFT innovation, automation, and technical tradeoffs while mentoring senior engineers and influencing customers, partners, and senior stakeholders.
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

What you'll need

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of relevant experience; or bachelor's degree with 15+ years of relevant experience.
• Exceptional mastery of SoC DFT and demonstrated recognition as a senior technical authority across programs or technical areas.
• Expert-level experience with scan and ATPG, compression, memory test and repair, test clocking and access, boundary scan, and hierarchical DFT.
• Experience defining DFT implementation, verification, readiness, and signoff criteria across IP, subsystem, partition, and SoC levels.
• Experience across the silicon lifecycle, including architecture, RTL integration, physical implementation, pattern generation, tapeout, silicon bring-up, and high-volume manufacturing.
• Deep understanding of fault models, test coverage, diagnosis, outgoing quality, test time, manufacturing risk, and test cost.
• Experience with major DFT EDA toolchains (prefer SNPS) and automation using Python, Tcl, Perl, Shell, or equivalent languages.
• Demonstrated ability to solve exceptionally complex problems, lead across organizational boundaries, influence senior stakeholders, and communicate technical and business tradeoffs.

Nice to have

• Experience with advanced DFT methodologies such as hierarchical ATPG, streaming scan, logic BIST, scan diagnosis, cell-aware test, or lifecycle test.
• Experience with memory repair, NVM test, eFuse, IEEE 1149.1 boundary scan, IEEE 1687 IJTAG.
• Experience with low-power, tester-correlation, silicon-debug, and high-reliability DFT requirements.
• Track record of developing reusable DFT architectures, automation, reference flows, and signoff methodologies across multiple SoC programs.

Details

• Location: Bengaluru, Karnataka, India.