Overview
Principal Engineer, Design for Test (DFT), within the Connectivity Business Unit, leading DFT architecture, implementation and signoff for complex SoC and ASIC designs.
What you'll do
- Define and drive DFT architecture and implementation strategies for complex SoC/ASIC designs.
- Develop and implement scan, compression, MBIST, and other DFT features to achieve test coverage and manufacturing quality goals.
- Execute and support scan insertion, DFT verification, and ATPG flows.
- Collaborate closely with RTL, verification, physical design, timing, and product engineering teams throughout the design lifecycle.
- Create and maintain DFT-related timing constraints and signoff requirements.
- Perform DFT timing analysis and debug timing-related issues.
- Drive DFT methodology improvements and contribute to flow automation.
- Provide technical leadership and mentorship to junior engineers.
What you'll need
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
- 14+ years of experience in Design for Test (DFT) for ASIC/SoC development.
- Strong expertise in DFT methodologies, including scan architecture, scan compression, ATPG, Memory BIST, Boundary Scan and testability concepts.
- Hands-on experience with Siemens EDA Tessent tools.
- Strong experience with synthesis and scan insertion tools.
- Solid understanding and hands-on experience of Static Timing Analysis (STA) and timing closure concepts.
- Experience creating and managing SDC (Synopsys Design Constraints) files for DFT implementation and timing signoff.
- Strong debugging, problem-solving, and analytical skills.
- Excellent communication and collaboration skills.
Details
- Eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers.
- Role may require access to export-controlled technology under U.S. EAR; applicants may be subject to an export license review process prior to employment unless U.S. citizen, lawful permanent resident, or protected individual.
Read the full description and apply on the company’s own careers page.