NPU Staff Design Verification Engineer

Overview

Qualcomm is hiring a Staff Design Verification Engineer to verify complex proprietary DSP/NPU IP, supporting high-performance DSP/NPU cores used across Qualcomm's multi-tier SoC roadmap for mobile, AI, automotive and more.

What you'll do

• Drive design verification of DSP IP by working with a global DSP design team including architecture, implementation, power, post-silicon and back-end teams.
• Implement and improve System Verilog/UVM testbench architecture.
• Develop and deploy new verification methodologies and automation to continuously improve quality and efficiency.
• Develop design-corresponding test plans, architect and develop verification environments, and meet coverage goals.
• Perform hands-on simulations and debug IP-level, subsystem-level and SoC-level fails and bugs.
• Complete all required verification activities at IP level to ensure high quality of commercial products.
• Use assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration and emulation on a daily basis.
• Be responsible for gate-level simulation bring-up and gate-level verification with timing simulations.
• Be responsible for power-aware RTL verification and gate-level simulation.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience, OR Master's degree in the same fields and 5+ years of Hardware Engineering or related work experience, OR PhD in the same fields and 4+ years of Hardware Engineering or related work experience.
• 12+ years of experience in processor/ASIC design verification.
• Solid background and understanding of Digital Design, Processor Architecture, Processor Verification and Power-aware verification.
• Expertise in System Verilog testbench architecture and implementation.
• Experience with Gate-Level Simulation and Debug: 0-delay, timing annotated and power-aware.
• Experience in System Verilog/UVM and with simulators from Synopsys/Mentor/Cadence.
• Scripting/automation skills in Perl, Python, Shell and Makefile TCI.
• Solid analytical and debugging skills, strong knowledge of digital design, and good understanding of Object Oriented Programming (OOP) concepts.
• Excellent inter-personal and communication skills.

Nice to have

• Experience writing C-based and assembly-level testcases.
• Exposure to power-aware implementation and verification using UPF.
• Experience with advanced verification techniques such as formal and assertions.
• Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC, and hardware description languages (HDL) such as Verilog and SystemVerilog.
• Experience in verification of processor subsystems.
• Experience in creating validation suites and building automation.

Details

• Location: Bangalore, India.