CPU Design Sr Staff Verification Engineer

Overview

Verify power management features of high-performance, low-power CPUs as a Senior Staff Verification Engineer in Bangalore, working within the Qualcomm Hardware Engineering group.

What you'll do

• Verify power management features including boot, reset, clock gating, power gating, voltage/frequency management, limit management and throttling.
• Work closely with CPU design and verification teams to develop a comprehensive test plan.
• Use simulation and formal verification methodologies to execute test plans.
• Write checkers and assertions and develop stimulus.
• Verify power intent through methodologies such as UPF.
• Work closely with system architects, software teams and SoC team to validate system use cases.
• Work closely with the emulation team to enable verification on emulators and FPGA platforms.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• BE/BTech degree in CS/EE with 12+ years' experience.
• Experience in power management verification.
• Implementation of assembly and C language embedded firmware.
• Experience in C/C++, scripting languages, Verilog/SystemVerilog.
• Strong understanding of power management features in CPUs and CPU-based SoCs.
• Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Nice to have

• Good understanding of CPU architectures and CPU micro-architectures.
• In-depth knowledge of digital logic design, microprocessor, debug feature, and DFT architecture and microarchitecture.
• Experience with advanced verification techniques such as formal and assertions is a plus.
• Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus.

Details

• Location: Bangalore, India.