STA Engineer

Overview

STA Engineer to plan, design, verify, and test electronic/ASIC systems and support timing analysis and constraint-driven flows.

What you'll do

• Perform static timing analysis for ASIC designs using Primetime and/or Tempus.
• Generate and validate timing constraints.
• Execute Place & Route flow work using FC or Innovus.
• Support ASIC flow completion with low power, performance, and area optimization techniques.
• Implement and validate multiple power domain designs using UPF/CPF definitions.
• Apply formal verification experience using Formally/Conformal.
• Contribute to FPGA/DSP/CPU-related development and debugging and critical path work.

What you'll need

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years hardware engineering experience, OR Master’s with 5+ years, OR PhD with 4+ years.
• Extensive experience in Place & Route with FC or Innovus is required.
• Experience with STA using Primetime and/or Tempus is required.
• Proficiency in constraint generation and validation is required.
• Experience with complex UPF/CPF power domain implementation is required.
• Formal verification experience with Formally/Conformal is required.
• Skills in Perl/Tcl, Python, and C++ are needed.

Details

• Location: Hyderabad, Telangāna, India.