Overview
Staff/VLSI Design Engineering role focused on leading functional verification for complex IP blocks and full-chip SoC designs.
What you'll do
- Lead development and execution of verification test plans, strategies, and verification infrastructure.
- Design and implement verification environments using industry-standard UVM frameworks.
- Build reusable verification components such as bus functional models, monitors, checkers, and scoreboards.
- Drive functional coverage closure and ensure comprehensive design validation.
- Develop and maintain SystemVerilog Assertions (SVA) for design verification.
- Investigate failures, debug issues, and perform root-cause analysis through cross-functional collaboration.
- Mentor junior engineers and contribute to continuous improvement of verification methodologies.
What you'll need
- 8 to 12 years of relevant experience in VLSI design verification.
- Bachelor's degree in ECE, VLSI, or Electrical Engineering (Master's preferred).
- Advanced proficiency in C, Verilog, SystemVerilog, and UVM.
- Hands-on experience with Xcellium, Verdi, and JasperGold formal verification tools.
- Experience across the verification lifecycle including planning, testbench and test case development, regression management, coverage analysis, debugging, and sign-off.
- Proven ability to lead technical projects and manage stakeholder relationships.
Nice to have
- Experience with NAND flash memory protocols and memory design verification.
- Experience with formal verification methodologies and assertion-based verification.
- A track record of mentoring junior engineers and improving processes.
Details
- Location: Bengaluru, KA, India.
Read the full description and apply on the company’s own careers page.
