Principal Engineer

Overview

Principal Engineer role focused on leading verification for complex semiconductor designs, including defining strategies, building UVM/SV environments, and driving verification closure.

What you'll do

• Define verification architecture and strategy for IPs, subsystems, and SoCs.
• Develop constraint-random verification environments using SystemVerilog and UVM.
• Create reusable verification components, assertions, coverage models, and testbenches.
• Run and close verification across RTL, power-aware simulations, gate-level simulations, and boot verification.
• Verify ARM-based IPs/SoCs with AHB, AXI, and serial communication protocol knowledge.
• Develop C-based tests, debug using Tarmac, and collaborate with design and software teams.
• Drive automation to improve verification productivity, coverage, and quality.

What you'll need

• Strong expertise in Verilog/SystemVerilog, UVM, C programming, and Tarmac debugging.
• Proven experience in IP and SoC verification (planning, component development, assertion coding, constrained-random).
• Experience leading/contributing to verification architecture and UVM environment development from scratch.
• Hands-on experience in RTL verification, power-aware verification, gate-level simulation, and boot verification.
• Knowledge of ARM-based architectures and AHB/AXI protocols plus serial interfaces.
• Experience with verification automation, coverage closure, regression management, and signoff activities.
• Analytical, debugging, leadership, and stakeholder management skills to mentor engineers.

Details

• Location: Bangalore BTP.