System-verilog Questions Set 3:
Determine the function defined by the following Verilog code:
Solution:
The default value for register and net data types are respectively _______ and _______.
Solution:
Which one of the following is not a Finite State Machine (FSM) encoding option?
Solution:
The code given below is a Structural Description of a specific digital logic circuit.
Solution:
Which one of the following is not a Verilog control block or conditional statement?
Solution:
________ events are processed after all active, inactive and non-blocking assignments are done.
Solution:
Which of the following statements about the 'wire' data type are correct?
Solution:
Select the statement that is INCORRECT.
Solution:
What is the output of the following SystemVerilog code?
module test;
bit unsigned d1;
byte unsigned d2;
initial begin
d1 = {1{4'b1xz0}};
d2 = {5{1'b1}};
$display("%0d %0d", d1, d2);
end
endmodule
Solution:
What is the output of the following Verilog code?
module test;
int assoc_arr[int];
int i;
initial begin
assoc_arr[1] = 11;
assoc_arr[2] = 2;
assoc_arr.first(i);
$display(assoc_arr[i]);
$display(assoc_arr.prev(i));
end
endmodule
Solution:
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