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Vhdl Questions Set 8:

Quiz Mode

The entity name ‘xyz’ and ‘XYZ’ will be treated the same.

True

False

Solution:

Which of the following symbols are used for 'Commenting' a line in VHDL?

Solution:

What is the default type of ports in an entity in VHDL?

Variables

Constants

Signals

Functions

Solution:

Which of the following is NOT a mode of operation of a MOS Capacitor?

Inversion Mode

Depletion Mode

Accumulation Mode

Linear Mode

Solution:

What is the main purpose of using blocks in VHDL?

To improve reusability

To improve conditional execution

To improve readability

To improve speed of execution

Solution:

How can electromigration be reduced?

Increasing metal cross-sectional area

Reducing metal cross-sectional area

Decreasing current density

Using strong buffers

Solution:

In VHDL, what is the primary purpose of using Generics?

To describe the architecture accurately

To divide the code into smaller blocks called processes

To switch the drivers on and off

To pass information to the Entity

Solution:

Which are the two types of delay that VHDL offers to model the delays of practical logic gates?

Sigma delay & Transport delay

Propagation delay & Sigma delay

Sigma delay & Propagation delay

Inertial delay & Transport delay

Solution:

How many types/styles of description does VHDL/Verilog offer and what are they?

3 - (Data flow, Behavioural, Structural)

4 - (Data flow, Behavioural, Structural, Hierarchical)

6 - (Data flow, Behavioural, Structural, Switch level, Mixed type, Mixed language)

7 - (Data flow, Behavioural, Structural, Switch level, Mixed type, Mixed language, Hierarchical)

Solution:

Which of the following is an entity declared for a full adder?

ENTITY full_adder
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

<pre class="ql-syntax" spellcheck="false">ENTITY full_adder IS PORT(a, b, c : IN BIT; s, co : OUT BIT); END full_adder; </pre>

<pre class="ql-syntax" spellcheck="false">ENTITY full_adder IS PORT (a ,b : IN BIT; s, c : OUT BIT); END full_adder; </pre>

<pre class="ql-syntax" spellcheck="false">ENTITY full_adder IS PORT (a, b, c, s, co : BIT); END full_adder; </pre><p><br></p>

Solution:

Related Topics:

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Control-systems Questions Set 1

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Vhdl Questions Set 8:

The entity name ‘xyz’ and ‘XYZ’ will be treated the same.

Solution:

Which of the following symbols are used for 'Commenting' a line in VHDL?

Solution:

What is the default type of ports in an entity in VHDL?

Solution:

Which of the following is NOT a mode of operation of a MOS Capacitor?

Solution:

What is the main purpose of using blocks in VHDL?

Solution:

How can electromigration be reduced?

Solution:

In VHDL, what is the primary purpose of using Generics?

Solution:

Which are the two types of delay that VHDL offers to model the delays of practical logic gates?

Solution:

How many types/styles of description does VHDL/Verilog offer and what are they?

Solution:

Which of the following is an entity declared for a full adder?

Solution:

Related Question Sets:

Related Topics: