CPU SRAM Design Engineer

Overview

As a CPU SRAM Design Engineer, design, improve, and analyze digital circuits for memories. Own custom SRAM and RF designs from schematic capture through analysis and model generation, contributing to high-performance, energy-efficient, and scalable CPU designs.

What you'll do

• Develop custom digital circuits for high-speed and low-power SRAM designs.
• Perform schematic capture.
• Plan and supervise layout.
• Perform functional verification.
• Perform simulation and margin verification.
• Perform timing characterization.
• Perform analysis steps necessary to generate all deliverable collateral models.
• Interact with the CAD team to ensure proper and efficient model generation.
• Interact with the Physical Design team to resolve memory PPA challenges.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience, or a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 5+ years of such experience, or a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 4+ years of such experience.
• Bachelor of Arts/Bachelor of Science degree in Electrical Engineering.
• 5+ years of practical experience.
• Experience designing SRAM circuits.
• Experience with industry-standard custom design tools and flows.
• Experience with circuit simulation and Monte Carlo analysis.
• Experience with static timing analysis.

Nice to have

• Master of Science degree in Electrical Engineering.
• 7+ years of practical experience.
• Strong knowledge of SRAM and Register File techniques with advanced custom circuit implementations.
• Strong knowledge of high-performance and low-power design features and techniques.
• Strong knowledge of semiconductor device fundamentals.
• Familiarity with variation-aware simulation in FinFET and Nanosheet technology nodes.
• Experience with custom memory layout designs.
• Experience with all memory analysis steps, including design entry, functional verification, layout guidance, simulation, timing, power, and electrical characterization.
• Good understanding of physical implementation impact on circuit performance.
• Proficiency with NanoTime, Ansys EMIR analysis, ESP-CV, and Liberate power analysis.

Details

• Location: Bangalore, India.