Design Methodology – Principal DRAM Power Integrity Engineer

Overview

Principal DRAM Power Integrity Engineer responsible for developing and standardizing EMIR methodology across DRAM products and leading EM/IR and PDN analysis.

What you'll do

• Develop and standardize EMIR methodology across DRAM products for alignment and repeatability.
• Run static and dynamic EM/IR and PDN analysis using RedHawk, Totem, or other industry tools.
• Identify root-cause issues (e.g., high-resistance segments, insufficient via density, decap deficiencies) and recommend fixes.
• Leverage AI-based tools, agentic workflows, and automation frameworks for PDN analysis.
• Execute end-to-end EMIR flow from netlist preparation through simulation/debug to reporting and silicon correlation.
• Partner with cross-functional teams to understand switching behavior and standardize analysis expectations.
• Maintain dashboards to track EMIR results, monitor trends, and support signoff progression.

What you'll need

• Master’s degree in electrical or computer engineering.
• 8–14 years of experience in PDN / Power Integrity / EMIR analysis for advanced semiconductor or SoC designs.
• Hands-on experience with Ansys RedHawk or Totem for full-chip EM/IR verification and PDN analysis.
• Expertise in vectorless and dynamic/pattern-based IR-drop analysis.
• Ability to identify root causes of IR-drop issues and translate findings into actionable design/layout fixes.
• Experience performing SoC-level or chip-level EMIR signoff and supporting tapeouts.
• Familiarity with Make or similar automation frameworks for EMIR rollups.

Details

• Location: Hyderabad, Telangana, India.