Design Verification Architect

Overview

Lead the formal verification strategy for high-performance PCIe and UALink controller IP, combining formal verification expertise with protocol and microarchitecture knowledge in a hands-on technical leadership role.

What you'll do

• Define the formal verification architecture and methodology for PCIe and UALink controller IP.
• Develop block, subsystem, and end-to-end formal verification strategies spanning protocol engines and state machines, transaction and packet processing, flow control and credit management, ordering and dependency rules, replay, retry, recovery, and error handling, arbitration, scheduling, and resource management, power/reset and initialization sequences, and configuration and control logic.
• Identify areas where formal verification can provide stronger coverage than simulation, especially for corner cases, deadlocks, livelocks, starvation, ordering violations, data integrity, and protocol compliance.
• Architect assume-guarantee, compositional, abstraction, and formal decomposition strategies for large and complex controller designs.
• Develop reusable SystemVerilog Assertions (SVA), properties, checkers, constraints, and formal verification IP.
• Drive convergence of difficult proofs through abstraction, cut-points, state-space reduction, invariants, partitioning, and proof-debug techniques.
• Work closely with RTL architects and designers to improve design-for-formal-verification and resolve architectural ambiguities early.
• Define formal coverage criteria and establish metrics for proof completeness, unreachable states, vacuity, assumptions, and coverage closure.
• Lead formal analysis of complex bug classes that are difficult to expose through constrained-random simulation.
• Establish the appropriate balance between formal, simulation, emulation, and system-level verification.
• Review verification plans and architecture specifications to identify formal opportunities and verification gaps.
• Mentor verification engineers and raise formal verification capability across the broader controller verification organization.

What you'll need

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Typically 15+ years of verification experience.
• At least 5 years of significant hands-on formal verification experience.
• Deep expertise in property-based formal verification of complex RTL.
• Deep knowledge of PCI Express, preferably PCIe 5.0/6.0/7.0 controller architecture and verification.
• Experience with UALink, CXL, UCIe, Ethernet, or comparable high-performance interconnect protocols.
• Strong knowledge of SystemVerilog and SVA.
• Strong knowledge of formal property development.
• Strong knowledge of assumption and constraint modeling.
• Strong knowledge of abstraction and decomposition.
• Strong knowledge of formal coverage and proof closure.
• Strong knowledge of counterexample analysis and debug.
• Hands-on experience with industry formal platforms such as Cadence Jasper or equivalent.
• Experience applying formal verification to high-speed interconnect or networking controller designs.

Details

• Location: Bangalore, India.