DFT Engineer

Overview

DFT Engineer role in Qualcomm's ASICS Engineering group focused on RTL and gate-level verification at SoC level.

What you'll do

• Perform RTL/GLS verification at SoC level.
• Identify issues in RTL, netlist and timing databases and work with Design/PD teams.
• Work in Verdi and VCS for pre-silicon verification.
• Generate vectors and provide post-silicon validation support to TE teams.
• Develop C-based testcases and integrate them in SV UVM environment at SoC level.
• Understand core-level tests and create SoC-level test plans and test cases.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• Experience in RTL/GLS verification at SoC.
• Good in Verilog/SV and familiarity with basic concepts of UVM and C-based test case bring up.
• Experience in Python/Perl or any other scripting tools.
• Knowledge in GLS/SDF debugs and problem solving.
• Knowledge in JTAG protocols and Boundary Scan architecture verification.
• Knowledge in ARM-based SoC architecture.
• Knowledge in bus protocols (AHB, AXI, APB), serial protocols (I2C, SPI, UART) and peripherals (USB2/3, PCIE, UFS) PHYs.
• Debugging knowledge from assertions/waveform dumps.
• Good communication skills.

Details

• Location: Bangalore, India.
• Experience level: Engineer, Senior (2-5 years).