Director, Physical Design (Custom Silicon Group)

Overview

Lead the development and delivery of next-generation, high-performance SoCs from concept to tapeout as an ASIC Design Manager (Principal / Director-Level) in the Custom Silicon Group, serving as a customer-facing engineering leader.

What you'll do

• Drive the complete silicon development lifecycle, spanning architecture, RTL design, integration, physical design, verification, silicon bring-up, and production readiness.
• Lead and manage a team across multiple functions.
• Demonstrate proven experience in executing responsibilities across multiple sites.
• Shape the physical design strategy, ensuring design convergence and maintaining signoff integrity across timing, power, and area metrics.
• Take complete ownership of PnR implementation, including floor planning, placement, CTS, and post-route activities on cutting-edge nodes.
• Collaborate effectively to resolve issues related to constraints validation, verification, STA, physical design and tapeout.
• Understand deep sub-micron design challenges, including leakage power, signal integrity, and DFM.
• Support pre-sales and business development activities by evaluating technical feasibility and providing design expertise.
• Provide technical leadership during design reviews and executive-level customer engagements.
• Drive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams.
• Partner with strategic customers and stakeholders to translate business requirements into successful silicon solutions.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience, or Master's degree in the same fields and 7+ years of Hardware Engineering or related work experience, or PhD in the same fields and 6+ years of Hardware Engineering or related work experience.
• Bachelor's or Master's degree in Electrical/Electronics Engineering and 20+ years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs.
• Design closure and tapeout expertise in advanced technology nodes.
• Mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV.

Nice to have

• Excellent hands-on experience on Floor planning, PnR and STA flows.
• Good knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc.
• Thorough understanding of signoff domains: LEC/CLP/PDN etc.
• 18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm).

Details

• Location: Bangalore, India.