Engineer, DDEG Design Methodology

Overview

Engineer role focused on DRAM design verification methodology and environments, using simulation, debugging, and AI-driven automation/workflows.

What you'll do

• Assist with overall verification activities for DRAM design and related product opportunities.
• Accelerate verification cycle time using AI-based tools, agentic workflows, and automation frameworks.
• Simulate, analyze, and debug pre-silicon block level and full chip designs.
• Develop and maintain test cases/stimulus and test benches/test vectors for functional coverage.
• Run regressions for coverage analysis and improvements using an agentic AI flow.
• Co-work with international colleagues to develop new verification flows.
• Participate in developing verification methodology and verification environments for advanced products.

What you'll need

• Analytical capability for complex gate level circuit designs.
• Basic understanding of CMOS circuit designs.
• Familiarity with SPICE and Verilog simulations.
• Good communication skills.
• Ability to work well in a team.

Details

• Location: Hyderabad, Telangana, India.