Principal Engineer, Ddeg Design Method

Overview

Principal Engineer for DRAM design verification, owning end-to-end verification and analysis of full chip, gate-level custom designs. Use AI-based tools and simulation to accelerate verification, improve debug efficiency, and increase test coverage.

What you'll do

• Accelerate verification cycle time using AI-based tools, agentic workflows, and automation frameworks.
• Validate AI outputs by reviewing assumptions, aligning with specs/standards, cross-checking with simulations/waveforms, and documenting decisions.
• Simulate, analyze, and debug pre-silicon block-level and full-chip designs.
• Develop test cases/stimulus to improve functional coverage for DRAM and emerging memory architectures.
• Develop and maintain test benches/test vectors and run regressions to analyze and improve coverage.
• Partner with international colleagues to develop new verification flows and verification methodologies/environments.

What you'll need

• Experience in SystemVerilog and PLI coding.
• Experience with UVM test bench development.
• Experience in DRAM/SRAM or other memory-related fields.
• Good understanding of digital/mixed-signal circuits and mixed-signal verification experience.
• Proficiency with tools including Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice.
• Previous experience with SPICE and/or Verilog simulations.