Principal Engineer, Ddeg Design Method

Overview

Principal Engineer responsible for full-chip, gate-level DRAM/memory verification and end-to-end analysis, using AI-based tools and automation to improve verification and debug efficiency.

What you'll do

• Use AI-based tools, agentic workflows, and automation frameworks to accelerate verification cycle time.
• Develop and support test-case/TB components for DRAM design verification.
• Validate AI outputs by reviewing assumptions, aligning with specs/standards, and cross-checking simulations and coverage.
• Simulate, analyze, and debug pre-silicon block level and full chip designs.
• Develop test cases and stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Build and maintain test benches/test vectors and run regressions for coverage analysis and improvements.
• Collaborate with international colleagues on new verification flows and verification methodology/environments.

What you'll need

• Experience in Digital/Mixed signal circuits and Digital/Mixed signal verification.
• Tool familiarity including Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice.
• Experience writing Verilog and Real Number Models (real number models is stated as a plus).
• Experience building SV testbenches at block and full-chip level.
• SV and UVM-based verification experience.
• Scripting skills in perl and python (python is stated as a plus).
• SystemVerilog, PLI coding, and UVM testbench experience (core qualifications).
• Strong communication and debugging skills, and ability to work in a team.

Details

• Location: Hyderabad - Phoenix Aquila, India.