Engineer, DDEG Design Methodology

Overview

Engineer role focused on DRAM Design (DDEG) verification methodology, environments, and pre-silicon simulation, analysis, debugging, and regression.

What you'll do

• Contribute to verification activities for DRAM design to support new product opportunities.
• Use AI-based tools, agentic workflows, and automation frameworks to accelerate verification cycle time.
• Develop and maintain test cases/stimulus and test benches/test vectors for functional coverage.
• Simulate, analyze, and debug pre-silicon block-level and full-chip designs.
• Run regressions for coverage analysis and improvements.
• Develop verification methodology and verification environments for advanced DRAM and emerging memory products.
• Co-work with international colleagues to develop new verification flows.

What you'll need

• Analytical capability for complex gate-level circuit designs.
• Basic understanding of CMOS circuit designs.
• Familiarity with SPICE and Verilog simulations.
• Good communication skills and ability to work well in a team.

Details

• Location: Hyderabad - Phoenix Aquila, India.