Lead Engineer – IC Design (STA Lead )

Overview

Lead Design Engineer (STA Lead) responsible for leading and executing BE/physical design timing activities, including constraints, synthesis, and Static Timing Analysis (STA) through GDSII sign-off for SoCs/ASICs.

What you'll do

• Develop, manage, and validate timing constraints for RTL-to-GDSII flow with Design and DFT teams.
• Own STA execution for digital blocks and top-level designs.
• Support CTS spec generation with Design and PnR engineers.
• Run Logical Equivalence checks and generate/interpret timing reports.
• Implement timing ECOs to resolve critical path issues.
• Execute end-to-end physical design flow from RTL handoff to GDSII and optimize PPA metrics.
• Lead the team and drive EDA tool flow automation and methodology enhancements.

What you'll need

• 7+ years of experience in ASIC physical design.
• Bachelor’s or Master’s degree in ECE, EEE, VLSI, or related field.
• Hands-on expertise in industry EDA tools (Cadence: Genus/Innovus/Tempus/LEC/CLP or Synopsys: ICC2/Fusion Compiler/PrimeTime).
• Strong background in synthesis, constraints, margins, and timing analysis/fixing.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements.
• Excellent problem-solving and communication skills.

Details

• Location: Hyderabad.