FPGA Silicon Design Verification Engineer

Overview

Design Verification (DV) Engineer to verify DFT and test-related logic for complex SoC and IP designs on FPGAs.

What you'll do

• Develop and execute pre-silicon verification plans for DFT and test-logic features.
• Create and maintain SystemVerilog/UVM-based verification environments.
• Build reusable verification components, sequences, scoreboards, assertions, and coverage models.
• Verify DFT architectures and test modes across IP, subsystem, and SoC levels.
• Run functional, regression, and coverage-driven verification.
• Analyze simulation failures, debug RTL/testbench issues, and drive root-cause resolution.
• Track verification metrics including functional coverage, code coverage, and regression results.

What you'll need

• 5+ years of ASIC/SoC design verification experience.
• Strong SystemVerilog and UVM expertise.
• Experience verifying DFT features such as scan insertion/compression, MBIST, LBIST, and JTAG/boundary scan.
• Strong debugging skills in simulation environments.
• Experience with VCS, Xcelium, or Questa simulators.
• Knowledge of SVA, constrained-random verification, and coverage-driven methodologies.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Details

• Shift: Shift 1.
• Primary location: Penang 15, Penang, Malaysia.
• Job type: Regular.