High Performance DSP core Implementation(Synthesis) Senior Staff Engineer

Overview

Senior Staff Engineer responsible for high-performance DSP core implementation, synthesis, timing closure, power optimization, and netlist delivery.

What you'll do

• Perform physical synthesis and synthesis optimization using industry-standard tools.
• Write timing constraints and support STA, timing closure, and pipelining.
• Optimize performance and timing across multi-clock domain designs.
• Handle MCMM synthesis, power optimization, and clock-gating flows.
• Collaborate with design, DFT, and physical design teams on netlist delivery and constraint validation.
• Handle ECOs and formal verification while maintaining quality metrics.

What you'll need

• 12+ years of hands-on experience in synthesis and LEC.
• Strong knowledge of physical synthesis and synthesis methodologies.
• Experience with UPF-based low-power design implementation.
• Proficiency in Python or Tcl scripting.
• Experience with Fusion Compiler or Genus synthesis tools.
• Knowledge of Verilog/VHDL, QoR optimization, and equivalence checking.
• Bachelor's, master's, or PhD degree in science, engineering, or a related field.

Nice to have

• Familiarity with version control, configuration management, and regression practices.

Details

• Location: Noida, Uttar Pradesh, India.