IP Design -Lead Engineer

Overview

Lead Engineer role focused on IP and SoC hardware design, integration, timing, low-power design, and pre- and post-silicon debug.

What you'll do

• Develop logic design, micro-architecture, and RTL code for SoCs.
• Design and integrate SoCs using Verilog and SystemVerilog.
• Develop constraints and perform timing closure.
• Collaborate with SoC verification and validation teams on pre- and post-silicon debug.
• Develop low-power SoC and multi-clock designs with asynchronous interfaces.
• Perform ASIC synthesis and timing analysis.
• Use ASIC development tools including Lint, CDC, Design Compiler, and PrimeTime.

What you'll need

• Bachelor's degree and 3+ years of Hardware Engineering or related experience.
• Master's degree and 2+ years of Hardware Engineering or related experience.
• PhD and 1+ year of Hardware Engineering or related experience.
• Hands-on experience with SoC design and integration.
• Knowledge of AMBA protocols, including AXI, AHB, and APB.
• Experience with low-power SoC design and ASIC timing concepts.
• Experience with multi-clock designs and asynchronous interfaces.

Nice to have

• Understanding of memory controller designs and microprocessors.
• Experience creating pad rings and working with chip-level floorplan teams.

Details

• Location: Chennai, Tamil Nadu, India.