Overview
Junior Design Verification Engineer to build and support ASIC verification environments for a new R&D center in Israel, validating next-generation AI silicon.
What you'll do
- Develop ASIC verification environments for unit-level and subsystem functional blocks.
- Create and maintain SystemVerilog/UVM verification components including traffic generators, monitors, and checkers.
- Execute verification plans to confirm functional requirements for digital designs.
- Build functional coverage models and analyze results to find verification gaps.
- Work toward verification closure using comprehensive test development.
- Debug hardware/verification issues by collaborating with design engineers and root-cause failures.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Strong understanding of digital logic.
- Experience with at least one programming language (C/C++ or Python).
- Basic familiarity with Verilog or SystemVerilog from academic projects or lab work.
- Attention to detail and a curiosity for finding bugs.
- Fluency in Hebrew and English to work effectively in a team.
Nice to have
- Master’s degree in Electrical Engineering or a related field.
- Proficiency in Python or Tcl scripting to automate verification tasks.
- Exposure to UVM/OVM or constrained-random verification.
- Basic understanding of PCIe, Ethernet, or DDR protocols.
Details
- Location: Israel (strategic R&D center).
Read the full description and apply on the company’s own careers page.
