Lead Design Engineer

Overview

Lead end-to-end RTL design and integration for complex SoC, subsystem, and IP blocks, from architecture interpretation to design closure.

What you'll do

• Own RTL design and development for SoC, subsystem, and IP blocks.
• Translate architecture and product requirements into micro-architecture and implementation plans.
• Develop Verilog/SystemVerilog RTL focused on correctness, reusability, and scalability.
• Lead design of key blocks including interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
• Drive block/subsystem integration and resolve interface, timing, and functional issues.
• Collaborate across verification, physical design, DFT, firmware, and architecture teams to ensure design quality and closure.
• Support debug and closure for design issues found in simulation, emulation, silicon bring-up, or customer use cases.

What you'll need

• 4 to 18 years of experience in SoC/subsystem/IP design.
• BE/BTech/ME/MTech qualification.
• 10 to 14 years of experience in digital design with exposure to IP, subsystem, and SoC development.
• Strong expertise in RTL design using Verilog/SystemVerilog.
• Good understanding of AMBA protocols such as AXI, AHB, and APB.
• Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows.
• Scripting experience in Python, Perl, Tcl, or Shell for automation.

Nice to have

• Exposure to low-power design methodologies including UPF/CPF.
• Experience leading small design teams or owning major subsystems in large SoC programs.

Details

• Location: HYDERABAD.