Senior Engineer II - Design

Overview

Senior Engineer II - Design will help design ASIC blocks for next-generation Microchip FPGA devices that support SoC functionality with RISC-V CPUs.

What you'll do

• Design ASIC blocks from architecture through production release.
• Customize and integrate third-party IP blocks into SOC.
• Create new ASIC blocks as required for SOC and integration.
• Design compiled memories and integrate them with SOC along with memory MBIST.
• Work across teams including DFT, PnR, and logic verification.
• Perform RTL simulations and debugging.

What you'll need

• 7+ years of professional experience in RTL design, linting, CDC, synthesis, and STA.
• Experience with block-level micro-architecture and RTL design of complex ASIC blocks.
• Experience in IP development from scratch and integration into SOC.
• Familiarity with Verilog/SystemVerilog coding and assertions with unit-level verification.
• Experience with digital flows including linting, CDC, RDC, synthesis, and STA.
• Understanding of microprocessors and on-chip bus structures and protocols (e.g., AXI, AMBA, peripheral interconnects).
• Bachelor’s (with Diploma in VLSI) or Master of Engineering or Engineering degree with VLSI design experience.

Nice to have

• Experience with PCIe or USB.
• Deep understanding of at least three of RISC-V or ARM CPUs Network on Chip bus/interconnect.

Details

• Location: Hyderabad, India.
• Travel time: 0% - 25%.