Low Latency FPGA Developer

Overview

Design, implement, and test RTL (VHDL/Verilog) for FPGA-based systems used in high-frequency trading to reduce system latency and improve performance.

What you'll do

• Develop high-performance RTL designs using VHDL or Verilog for FPGA-based systems.
• Optimize hardware implementations for ultra-low latency and high throughput.
• Run functional and timing testing to ensure RTL adherence to specifications.
• Debug and resolve issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim.
• Integrate FPGA solutions with the software trading stack alongside hardware and software teams.
• Maintain documentation for designs, test cases, results, and benchmarks.

What you'll need

• Strong fundamentals in digital logic design, Boolean algebra, FSMs, and synchronous design.
• Proficiency in VHDL or Verilog/SystemVerilog for efficient and optimized designs.
• Hands-on experience with Xilinx Vivado.
• Expertise in writing testbenches and simulation-based verification.
• Familiarity with static timing analysis and achieving timing closure.
• Experience with CocoTB or similar testing setup.
• Ability to use Git, Makefiles, and automation scripts.

Details

• Location: Gurugram, Haryana, India.