NOC DV Staff Engineer

Overview

As a NOC DV Staff Engineer, you will lead verification of next-generation Infrastructure IPs used in System-on-chip (SoC) designs for smartphones, tablets, and other product categories.

What you'll do

• Plan and implement IP/cluster/formal verification flows for Infra IPs.
• Own the DV test bench and related verification collateral (checkers, trackers, scoreboards, assertions, functional coverage).
• Develop test plans and test cases to cover the design feature set and drive coverage closure.
• Coordinate with Design and SOC teams across the IP development cycle and manage failure debugs.
• Debug regression signatures and identify bug fixes.
• Collaborate on debug/root-cause analysis for post-silicon issues with Design, SW, and test teams.
• Develop or deploy validation scripts/tools (e.g., Certitude, VC Formal, VPlan).

What you'll need

• Have a Bachelor’s degree in CS/Electrical/Electronics/Engineering and 4+ years of hardware engineering experience, OR a Master’s with 3+ years, OR a PhD with 2+ years.
• Be experienced in IP verification (also stated as 8 years in the qualification section).
• Use expertise in UVM-based verification.
• Know ARM bus protocols, virtual memory concepts, and SoC system architecture.
• Build monitors/scoreboards/sequencers using SystemVerilog and UVM (and related methodologies).
• Have strong debugging, analytical, and problem-solving skills.
• Have scripting experience for automation (Python or Perl) and C/C++/SystemC exposure for performance models.

Details

• Location: Bangalore, India.