Physical Design - Engineer

Overview

Physical implementation of sub-systems, covering floor-planning, place and route, clock tree synthesis, formal verification, physical verification, power delivery network, timing closure and power optimization.

What you'll do

• Carry out physical implementation activities for sub-systems, including floor-planning, place and route, CTS, formal verification, physical verification (DRC/LVS), PDN, timing closure and power optimization.
• Make PPA trade-off decisions for PPA-critical cores.
• Drive timing convergence of high-frequency, data-path-intensive cores using advanced STA concepts.
• Achieve block-level PnR convergence with Synopsys ICC2 / Cadence Innovus and timing convergence in PTSI / Tempus in latest technology nodes.
• Work in close collaboration with design, DFT and PNR teams and resolve issues related to constraints validation, verification, STA and physical design.
• Use Tcl / Perl scripting.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• 3-6 years of experience.
• Good exposure to PD implementation of PPA-critical cores.
• Knowledge of timing convergence of high-frequency data-path-intensive cores and advanced STA concepts.
• Well versed in block-level PnR convergence with Synopsys ICC2 / Cadence Innovus.
• Well versed in timing convergence in PTSI / Tempus in latest technology nodes.
• Good understanding of clocking architecture.
• Well versed with Tcl / Perl scripting.
• Strong problem-solving skills and good communication skills.

Details

• Location: Chennai, Tamil Nādu, India.